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A high level language abstraction for reconfigurable computing

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  1. Abstract
  2. Introduction
  3. Current systems
  4. Where is RC important today?
  5. Reconfigurable computing
  6. External visible internal state
  7. Run time environments
  8. Three layer archtecture of run time environmemnt
  9. Rate of reconfiguration
  10. Tool flow
  11. Looking forward
  12. Refrences

The gain of SVC depends upon the type of reactive power load for optimum performance. As the load and input wind power conditions are variable, the gain setting of SVC needs to be adjusted or tuned. In this paper, an ANN based approach has been used to tune the gain parameters of the SVC controller over a wide range of load characteristics. The multi-layer feed-forward ANN tool with the error back propagation training method is employed. Loads have been taken as the function of voltage. Analytical techniques have mostly been based on impedance load reduced network models, which suffer from several disadvantages, including inadequate load representation and lack of structural integrity. The ability of ANNs to spontaneously learn from examples, reason over inexact and fuzzy data and provide adequate and quick responses to new information not previously stored in memory has generated high performance dynamical system with unprecedented robustness. ANNs models have been developed for different hybrid power system configurations for tuning the proportional-integral controller for SVC. Keywords: Performance analysis, profile, trace, reconfigurable computing,FPGA,high level language, C, Carte, Reprogrammability, Recongigurable, hardware, Granularity, Hardware Object

[...] Though these features are compatible with configurable computing applications, they are not sufficient for reconfigurable computing. In order to benefit from run-time reconfiguration, it is necessary that the FPGAs involved have some or all of the following features. The more of these features they have, the more flexible can be the system design. ON THE FLY REPROGRAMMABILITY Whenever possible, we'd like to avoid resetting the FPGA, mostly because it takes a lot of time. Ideally, we could just stop the clock going to some or all of the chip, change the logic within that region, and restart the clock. [...]


[...] It was not a commercial success, but was promising enough that Xilinx (the inventor of the Field-Programmable Gate Array, FPGA) bought the technology and hired the Algotronix staf CURRENT SYSTEMS Currently there are a number of vendors with commercially available reconfigurable computers aimed at the high performance computing market; including Cray, SGI and SRC Computers, Inc . The reconfigurable computers are "Estrin" hybrid computers with microprocessors that can be used in traditional CPU cluster computers or coupled to user-programmable FPGAs for hybrid computing. [...]


[...] Much as there is a market for commercial operating systems for CPUs, we expect a market for commercial runtime environments for RPUs will emerge if reconfigurable computing becomes popular. That would save system designers even more time by allowing them to purchase a run-time environment rather than design their own. At that point, system design becomes a matter of purchasing or developing the required hardware object libraries, configuring a third-party run-time environment, and writing the application software--a truly efficient system development paradigm. [...]

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