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Cache coherence – survey

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profssional comp scientist
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  1. Introduction
  2. Cache Coherence Problem - An Analysis
  3. Cache Coherence Protocol
  4. Conclusion

Many multiprocessor chips and computer systems today have hardware that supports shared-memory. This is because shared-memory multicore chips are considered a cost-effective way of providing increased and improved computing speed and power since they utilize economically interconnected low-cost microprocessors. Shared-memory multiprocessors utilize cache to reduce memory access latency and significantly reduce bandwidth needs for the global interconnect and local memory module. However, a problem still exists in these systems: cache coherence problem introduced by local caching of data, which leads to reduced processor execution speeds. The problem of cache coherence in hardware is reduced in today's microprocessors through the implementation of various cache coherence protocols. This article reviews literature on cache coherence with particular attention to cache coherence problem, and the protocols-both hardware and software that have been proposed to solve it. Most importantly, it identifies a specific problem associated with cache coherence and proposes a novel solution.

[...] Fig illustrates a cache coherence problem. Initially, the memory has location x marked with value and both processors 1 and 0 are reading into their caches the location x. Processor 1 cache will contain a value 0 for the location x in the event that the location x is written into the value 1 by processor 0. If processor 1 continues to subsequently read location then the cached, stale value 0 will continuously be returned. Normally, this is not what a programmer expects since the anticipated behavior is that, for any read, a processor needs to return the most updated copy of the data. [...]


[...] In the event that a cache discovers a read request on the bus, it checks to find out whether it is the most up-to-date copy of the datum; if so, it responds to the bus request. In the event that the cache finds out that there is a write on the bus, if a line is present, it is invalidated out of the cache. Building snoopy bus-based systems are very easy (Ferdman et al., 2012). However, an increase in the number of processors on a bus results in a bandwidth bottleneck, which, in turn, makes dependence on broadcast techniques a scalability nightmare. Snoopy protocols are commonly used in commercial multicore processors. [...]


[...] These problems have been addressed by the adoption of distributed shared memory architecture (DSM) where each multiprocessor node contains a processor, a portion of the system's physical distributed memory, its caches and a node controller (Lai, Liu, Wang, & Feng, 2012). The node controller is responsible for managing communication between and within nodes. Instead of the nodes being connected by a share bus, they connected using an interconnection network that is scalable. This allows multiprocessors to be able to scale to thousands of nodes. However, due to the fact that a broadcast medium is lacking, there is a problem for snoopy bus-based protocols a cache coherence protocol ?which have become inappropriate. [...]


[...] This article reviews literature on cache coherence with particular attention to cache coherence problem, and the protocols-both hardware and software that have been proposed to solve it. Most importantly, it identifies a specific problem associated with cache coherence and proposes a novel solution. Keywords: microprocessor, latency, cache coherence, bandwidth, multiprocessor, cache coherence protocol, shared memory, multicore processor Introduction Currently, there is undeniable interest in the computer architecture domain with regard to shared-memory multiprocessors. Often, proposed multiprocessor designs include a reserved cache for each processor within the system. This, in turn, results in the cache coherence problem (Cheng, Carter, & Dai, 2007). [...]


[...] Cache coherence protocol is a distributed algorithm that has been used by multiprocessor architects to deal the problem of cache coherence (Archibald & Baer, 1986). Different types of cache coherence protocol have been discussed and designed. It has been noted that these protocols have an impact on the performance of multiprocessors a parameter that is normally very difficult to estimate. A system's performance is considered to be in direct proportionality with a microprocessor's access latency. This paper reviews literature on cache coherence with particular attention to cache coherence problem, and the protocols, both hardware and software that have been proposed to solve it. [...]

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