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The main architectural features of the RISC (Reduced Instruction Set Computer)

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  1. Introduction.
  2. RISC processors: An overview
  3. RISC architecture
  4. Instruction sets and formats used
  5. Registers in RISC
  6. Instruction level pipelining.
  7. Comparison of RISC and CISC
  8. Conclusion
  9. Works cited

The world of computer technology has evolved rather rapidly in the past two decades. Interestingly, while the number of languages and programs available has increased, the specific architectures that are used for building microprocessors have not changed that dramatically. What this effectively suggests is that when one looks at the evolution of computers and computer technology, some degree of congruence and similarity can be seen, especially with respect to the specific architecture being utilized.With the realization that computer architecture has not changed that drastically in recent years, there is a clear impetus to examine this issue and explore why this has been so. Utilizing this as a basis for investigation, this research considers the main architectural features of the RISC, or reduced instruction set computer, processor. Specifically, this research considers RISC characteristics, instruction set and formats used, use of register files, instruction level pipelining, RISC processor selection and the advantages and disadvantages of RISC.

[...] Despite the overall utility and viability of RISC, it is clear that this technology is indeed reaching a pinnacle. This is due, in part, to the fact that methods for optimizing the technology have not advanced in recent years. In short the overall speed of the microprocessor has not increased drastically overall. As this technology reaches its apex, it is clear that a new microprocessor architecture will be born. For now it is just a matter of waiting for this new technology to be introduced. [...]


[...] Rather, RISC is indicative of the overall method by which commands are processed by the CPU (?Reduced instruction Finally, in order to make RISC systems efficient and ensure that most commonly used commands large register files are necessary to ensure efficiency. When one considers the overwhelming number of commands that are carried out by the computer and further considers these issues in the context of the ability of the CPU to access these commands, it only stands to reason that large a large number of registers would be necessary to carry out operations in the RISC system. [...]


[...] However, as researchers note the architectural design of the RISC processor has placed a notable burden on software developers. In the late 1980s, when computer companies could produced RISC processors cheaply, there was a dearth of computer software programs available for use on these machines. During this same time the CISC architecture was developed. Its central drawbacks involved both speed and cost issues. Today, because of the advancements that have been made in computer technology, the CISC model has become a viable alternative to the RISC model. [...]

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