A common problem for today's system designers is to reliably interface with their next generation high-speed memory devices. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. As a result, these next generation memory interfaces are also increasingly challenging to design too. Implementing high-speed, high-efficiency memory interfaces in programmable logic devices such as FPGAs has always been a major challenge for designers. Lattice Semiconductor offers customers a
high performance FPGA platform in the Lattice SC to design high-speed memory interface solutions. The LatticeSC family implements various features on-chip that facilitate designing high-speed memory controllers to interface to the next generation high-speed, high performance DDR SDRAM, QDR SRAM, and emerging RLDRAM
[...] The controllers are full-featured, fully tested controllers, providing users a low-risk timeto-market solution for high-speed memory interfaces DDR and DDR2 SDRAM Controller Implementing high performance DDR memory interfaces requires careful design of the read and write interface blocks of the memory controller. DDR2 memory devices pose a bigger challenge due to their higher speeds and the bi-directional DQS signal. The LatticeSCM memory controller utilizes onchip PLLs and DLLs, along with programmable delay elements at the input buffers to align the DQS and DQ signals. [...]
[...] Computing and consumer applications require memory solutions like DRAM modules, Flash cards and others that are highly cost sensitive while delivering the performance targets for these applications. This white paper will focus primarily on memory applications in networking and communications. Memory can be on-chip or off-chip. Next generation FPGAs like the LatticeSC have several Megabits (up to 7.8 of RAM onchip. These are useful for simple FIFO structures for nominal buffering requirements. Cost is the primary factor defining the amount of memory on-chip. [...]
[...] This is a major challenge in FPGA architectures. PLLs and DLLs and low-skew clock networks on-chip are essential to allow control of the clock-data relationship I/O Support Next-generation memory controllers operate at HSTL (High-Speed Transceiver Logic) or SSTL (Stub-Series Transistor Logic) voltage levels. This lower voltage level swing is required to support high-speed data operation of the inputs and outputs of the memory device (and the memory controller). HSTL is the de facto I/O standard for high-speed SRAM memory devices, while SSTL is the de facto I/O standard for high-speed DDR SDRAM memories. [...]
[...] Methods such as using the matched trace delays or preset input delay blocks can be used to delay the CQ with respect to the data, but using the DLL to delay the CQ signals by gives the greatest timing margin over PVT and is independent of the interface speed Embedded Memory Controller Advantages The embedded memory controllers on the LatticeSCM devices provide customers with high-performance, low-risk solutions for interfacing to their external memory chips. Customers do not need to design a memory controller using FPGA gates, saving time and FPGA real estate while designing high-speed designs requiring high-speed external memory interfaces. [...]
[...] A DLL is used to delay the QK signals by giving the user the greatest timing margin over PVT; this is also independent of the interface speed Essentially, the same read interface as DDR2 is used without the need for DQS postamble shut-off or preamble edge detect. The main difference is the higher speed of RLDRAM, up to 400 MHz, and the optional use of the high-speed I/O gearing logic QDR SRAM Memory Controller QDR SRAMs are very popular in low latency applications requiring simultaneous reads and writes. [...]
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